The present integrated circuit fabrication techniques, where components are fabricated in the semiconductor substrate horizontally along the surface of the semiconductor substrate, are approaching insurmountable limitations in reducing the size of devices so formed. Lithographic techniques are being limited by fringing effects of even ultraviolet light and closely spaced horizontal field effect transistors are proving more and more prone to latchup. Consequently it is an object of the present invention to provide a technique which circumvents these problems.
One solution developed for individual field effect transistors is the use of vertical structures. Examples of these are Chang et al. Vertical FET Random-Access Memories with Deep Trench Isolation, IBM Technical Dislosure, Vol 22, No. 8B. January 1980 and copending application Ser. No. 679,663, filed Dec. 7, 1984, abandoned Oct. 14, 1987, which are hereby incorporated by reference. However, prior techniques for fabricating vertical transistors only apply to single transistors of a selected single conductivity type. Thus the use of CMOS, with it low power consumption and small logic cell layout size, using prior vertical transistor fabrication techniques is difficult if not impossible.